The present invention relates to a power-on reset circuit, for logic devices, particularly logic arrays associated with microprocessors and the like, in which the array is required to come up with its outputs and other internal circuits immediately reset to desired logic states. More specifically, the invention relates to such a circuit for application to MOS technology integrated devices.
In logic arrays, such as, typical peripheral units operating under the control of microprocessors, or in the microprocessors themselves, it is often required that, immediately as the power is switched on, any internal logic states not compatible with an immediate operation of the interface is removed.
In such circumstances it is necessary that the array is reset before the supply voltage applied to the logic array reaches a level such as to put the array in operation.
To this purpose, the array (typically an integrated circuit) is provided, as is known, with a reset pin, to which an outside circuit sends a suitable reset signal (usually a positive voltage pulse which, after carrying out its function, falals back to a low level).